Objective VHDL is VHDL extended for object-orientation. It is expected to enable designers to model hardware at a higher level of abstraction compared to the present situation, and to support the reuse of hardware designs. System level descriptions are in particular targeted by Objective VHDL, which does not mean the application of object-oriented concepts was limited to this domain. Rather, it should also be possible to gain from Objective VHDL in terms of modelling and maintenance efficiency during refinement towards descriptions closer to implementation.
Requirements to the design of Objective VHDL have been compiled from REQUEST partners' contributions in deliverable [WP 1.2B] on design methodology and tool architecture. They include to target a higher level for modelling, to simplify and speed up the process of specification, to ease the addition of new functionality, and to improve the degree of reusability.
From these requirements, more concrete design objectives have been derived and shown to support meeting users' requirements. Major design objectives are the integration of a class concept, class inheritance, type polymorphism, and method call or message passing into VHDL, thereby making VHDL object-oriented while keeping VHDL concurrence.
The design objectives do not constrain object-oriented extensions to either the VHDL design entity or the VHDL type system. These alternatives do not exclude each other, and arguments have been found for both of them. Since they moreover became apparent to complement one another, the Objective VHDL language architecture has been described in [WP 1.2C] to provide extensible design entities as well as a class type.
The purpose of this document is to define Objective VHDL grammar and semantics. It will serve as language reference manual for the users and the developers of Objective VHDL parser, analyser, and to-VHDL-translator. We also expect to bring it in as contribution to the standardization efforts of the IEEE Working Group on object-oriented extensions to VHDL.
This document is structured as follows: In the next chapter we address the technical aspects arising from the task of extending VHDL and explain the style of language definition we have chosen. Chapter three defines syntax changes to the VHDL design entity and semantics associated with the new constructs. The fourth chapter comprises analogously the object-oriented extensions to the VHDL type system.